The present invention relates to information storage devices. More specifically, the present invention relates to a data storage device including a resistive cross point memory cell array.
Consider the example of a Magnetic Random Access Memory (xe2x80x9cMRAMxe2x80x9d) device including a resistive cross point array of spin dependent tunneling (SDT) junctions, word lines extending along rows of the SDT junctions, and bit lines extending along columns of the SDT junctions. Each SDT junction is located at a cross point of a word line and a bit line. The magnetization of each SDT junction assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of xe2x80x980xe2x80x99 and xe2x80x981.xe2x80x99 The magnetization orientation, in turn, affects the resistance of the SDT junction. Resistance of the SDT junction is a first value (R) if the magnetization orientation is parallel and a second value (R+xcex94R) if the magnetization orientation is anti-parallel. The magnetization orientation of the SDT junction and, therefore, its logic value may be read by sensing its resistance state.
Sensing the resistance state of a single SDT junction in a resistive cross point array can be unreliable. All SDT junctions in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the SDT junction at that cross point in parallel with resistances of SDT junctions in the other rows and columns.
Moreover, if the SDT junction being sensed has a different resistance state due to the stored magnetization, a small differential voltage may develop. This small differential voltage can give rise to parasitic or xe2x80x9csneak pathxe2x80x9d currents. The parasitic currents can interfere with the sensing of the resistance states.
Parasitic currents are illustrated in FIG. 1. A selected SDT junction is represented by a first resistor 12a, and unselected SDT junctions are represented by second, third and fourth resistors 12b, 12c and 12d. The selected SDT junction lies at the cross point of selected word and bit lines 14 and 16. The second resistor 12b represents the unselected SDT junctions along the selected bit line 16, the third resistor 12c represents the unselected SDT junctions along the selected word line 14, and the fourth resistor 12d represents the remaining SDT junctions. If, for example, all of the SDT junctions 12 have a nominal resistance of about R and if the array 10 has n rows and m columns, then the second resistor 12b will have a resistance of about R/(nxe2x88x921), the third resistor 12c will have a resistance of about R/(mxe2x88x921), and the fourth resistor 12d will have a resistance of about R/[(nxe2x88x921)(mxe2x88x921)].
During a read operation, the first resistor 12a may be selected by applying an operating potential Vs to the selected bit line 16 and a ground potential to the selected word line 14. Consequently, a sense current Is flows through the first resistor 12a. However, the second, third and fourth resistors 12b, 12c and 12d are also coupled between the operating potential Vs and the ground potential; therefore, sneak path currents S1, S2 and S3 can flow through the second, third and fourth resistors 12b, 12c and 12d. Moreover, the resistances of the second, third and fourth resistors 12b, 12c and 12d are much smaller than the resistance of the selected (first) resistor 12a; therefore, the sneak path currents S1, S2 and S3 are larger than the sense current Is. Such sneak path currents S1, S2 and S3 can obscure the sense current Is during a read operation on the selected SDT junction.
There is a need to reliably sense the resistance states of memory elements in MRAM devices. More generally, there is a need to reliably sense the resistance states of memory elements in resistive cross point memory cell arrays.
According to one aspect of the present invention, a random access memory device includes a resistive cross point array of memory elements, and a sneak path blocking device coupled to the memory elements. The blocking device is shared by a group of the memory elements. Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.